Fully-Integrated DLL/PLL-Based CMOS Frequency Synthesizers for Wireless Systems
نویسندگان
چکیده
I am grateful of Dr. Joy Laskar who guided and taught me with his endless energy and encouragement. I would like to thank Dr. Kyutae Lim and Dr. Woonyun Kim for their advice and support for my research. I am greatly indebted to the members of the Microwave Applications Group (MAG) for their assistance and cooperation, especially to cognitive radio (CR) team members. I also owe special thanks to the senior engineers in Samsung Design Center for helpful discussion and encouragement. To my parents, who have been shown great love and support in my life, I would like to express my deepest love and thank to them. Figure 36. Delay cells adopted in the VCDL (a) proposed delay cell (b) conventional Maneatis load delay cell [31].. Figure 37. Time transient simulation on generating 920 ps time-delay of the proposed delay cell and the conventional delay cell with a Maneatis load.. Figure 39. Anti-harmonic Start-controlled circuit (a) schematic (b) timing diagram of the
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